The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SOCs. The subsystem contains a flexible Power Management Unit that controls the power sequence of the CPU as well as the APB peripherals. The PMU can easily be extended to control additional cores, peripherals and even mixed signal subsystems on the same SOC.
The AHB Low Power Subsystem includes a standard set of peripherals and cores that supports RTOS and software kernels. The package includes software for boot code, interrupt handlers and driver code.
The AHB Low Power Subsystem is soft IP that can be used in all the popular semiconductor technology nodes.
AHB Low Power Subsystem - ARM Cortex M0
Overview
Key Features
- Low Power
- RTOS/Kernel Support
- AMBA AHB 2.0
- AMAB APB 3.0
- Power Management Unit
- Multiple Power Domains
Benefits
- Quick design start
- Integration expertise and support
- Hardware/Software and application support
- Cost effective
Block Diagram
Applications
- IoT Edge Devices
- Small Controllers
- Mixed Signal Digital - MEMS
- Smart Sensors
- Smart Lighting
- Health Monitors
- Power Management
- Industrial Sensors
Deliverables
- Verilog RTL source code
- Test bench with test suites
- Documentation including User's Guide and Integration Guide
- Technology-independent synthesis constraints
Technical Specifications
Foundry, Node
all
Maturity
Silicon Proven
Availability
Now
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- AHB Performance Subsystem - ARM Cortex M3
- AHB Secure Subsystem - ARM Cortex M3
- AXI Performance Subsystem - ARM Cortex A
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