Memory Controller for embeded systems supporting SDRAM and NandFlash, with bootstrap loader

Overview

RDEMC handles NandFlash and SDRAM, during RESET a bootstrap loader (512 Bytes) are copied from the NandFlash to the SDRAM. Thus eleminating the need of an extra Bootdevice. The RDEMC is therefore ideal for embedded systems. Flash and SDRAM can be connected to the controller with out glue logic. The RDEMC can handle up to 8 AHB interface therfore giving the integrator the utmost flexibility for his project.

Key Features

General

during RESET a block of 512 Bytes is copied from NandFlash to SDRAM

SDRAM Interface

Glueless connection to all JEDEC-compliant SDRAM
Shared data buses between SDRAM and NandFlash
Supports up to 13 SDRAM address bits
automatic detection of SDRAM Data width
Programmable parameters: 8 - 12 bit column address; 10 - 13 bit row address; CAS latency: 1-4 cycles; burst or single write; read pipeline: adds an extra latency cycle for external synchronization; actual timing (TRCD, TRP, TDAL, TRC, TWR); Supports 2 and 4 banks; Supports AutoRefresh and Powerdown

NandFlash Interface

Supports Samsung and Hitachi types
Supports 3 to 5 address bytes
Glueless connection of Flash
Data width 8 or 16 bit
Supports Powerdown

AMBA AHB Interface Features

AMBA V2.0 AHB bus-compatible
Supports the following AMBA features: nonsequential,sequential, idle and busy; single, INCR, INCR4, INCR8, INCR16, WRAP4, WRAP8, WRAP16
Supports AHB data widths of 32 bits
Supports AHB address width of 32 bits
Supports narrow access on wide AMBA bus
Does not generate split and retry responses on the AMBA bus
Up to 200MHz clock frequency

Benefits

~17.500 gates (1x AHB client, 1xSDRAM, 1xNandFlash)

Deliverables

Verilog RTL
Testbench
Synthesis Script
Manual

Technical Specifications

Availability

now

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