The Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an industry-standard FLASH or PSRAM memory device.
In Software Mode, an AHB Master may access the register interface of the Controller to implement a wide range of protocol variants and/or commands on the SPI bus. Programming options include transmission bit size, LSB/MSB first, SPI mode (the standard legacy 4-wire SPI bus interface or extended Dual, Quad or Octal Bus modes). Typical examples for software mode operations would be erasing and programming a FLASH device, or accessing the internal register set of a FLASH or PSRAM memory device.
The Execute in Place (XIP) Mode allows an AHB Master to directly read the contents of any of several industry-standard FLASH devices (such as Winbond, Macronix, Spansion and Micron devices) simply by reading from the address space of the OSPI Memory Controller.
The Bridge Mode allows an AHB Master to directly write to and read from the contents of any of several industry standard PSRAM devices (such as Infineon, APMemory). Supported standards for PSRAM devices include JEDEC JESD251A (Profile 2.0), HyperRAM and Xccela.
