Vendor: Silvaco, Inc. Category: SPI / QSPI XSPI

AHB Octal SPI Controller with PSRAM and XIP Support

The Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, u…

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Overview

The Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an industry-standard FLASH or PSRAM memory device.

In Software Mode, an AHB Master may access the register interface of the Controller to implement a wide range of protocol variants and/or commands on the SPI bus. Programming options include transmission bit size, LSB/MSB first, SPI mode (the standard legacy 4-wire SPI bus interface or extended Dual, Quad or Octal Bus modes). Typical examples for software mode operations would be erasing and programming a FLASH device, or accessing the internal register set of a FLASH or PSRAM memory device.

The Execute in Place (XIP) Mode allows an AHB Master to directly read the contents of any of several industry-standard FLASH devices (such as Winbond, Macronix, Spansion and Micron devices) simply by reading from the address space of the OSPI Memory Controller.

The Bridge Mode allows an AHB Master to directly write to and read from the contents of any of several industry standard PSRAM devices (such as Infineon, APMemory). Supported standards for PSRAM devices include JEDEC JESD251A (Profile 2.0), HyperRAM and Xccela.

Key features

  • Compatible with industry-standard FLASH devices
  • Compatible with PSRAM devices that conform to JEDEC JESD251A (Profile 2.0), HyperRAM, or Xccela standards
  • Supports in-band slave reset signaling defined by JEDEC JESD252
  • Software mode for direct control of registers
  • Execute-in-place (XIP) mode for supporting direct reads from industry-standard FLASH devices
  • Bridge mode for supporting direct writes and reads to/from industry standard PSRAM devices
  • Automated command transmission support when entering/exiting XIP or Bridge modes
  • AMBA AHB interfaces
  • DMA Interface
  • Interrupt control
  • Configurable (16, 32, 64) word Transmit/Receive FIFOs
  • Up to 4 slaves under Master control
  • 4, 8, 16 or 32 bit serial transmit and receive
  • Full duplex operation support
  • Half duplex operation support
  • DTR (Dual transfer rate) support
  • Octal (I/O x 8) operation
  • Quad (I/O x 4) operation

Block Diagram

AHB Octal SPI Controller with PSRAM and XIP Support block diagram

What’s Included?

  • Verilog Source
  • Complete Verilog Test Environment
  • AHB Functional Model

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
AHB Octal SPI Controller with PSRAM and XIP Support
Vendor
Silvaco, Inc.
Type
Silicon IP

Provider

Silvaco, Inc.
HQ: United States
Silvaco focuses on enabling the next generation of AI/ML, Cloud/Datacenter, Automotive and Autonomous Driving, IoT and 5G designs through a comprehensive offering of Silicon proven IP. Our portfolio includes a complete catalog of Interface IP, Amba Peripherals, Subsystems, MIPI IP and Automotive Communication Controller IP. Our experienced ASIC and Embedded Software designers have a rich history of designing SOCs with embedded microprocessors which are crucial to building small connected smart chips.
Contact Silvaco, Inc.

Learn more about SPI / QSPI XSPI IP core

Frequently asked questions about SPI / QSPI / xSPI IP cores

What is AHB Octal SPI Controller with PSRAM and XIP Support?

AHB Octal SPI Controller with PSRAM and XIP Support is a SPI / QSPI XSPI IP core from Silvaco, Inc. listed on Semi IP Hub.

How should engineers evaluate this SPI / QSPI XSPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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