The UMMC Controller is a highly flexible and configurable design. It is targeted for high bandwidth access and low power consumption such as next generation mobile, DDR/LPDDR networking and consumer applications. The controller architecture is carefully tailored to achieve reliable high-frequency operation with dynamic power management and rapid system debug capabilities.
UMMC Controller is part of Mobiveil's Storage and Memory controller family of IP solutions which also includes NVM Express (UNEX), Enterprise Flash Controller (EFC), and LDPC Controller IP cores.
The controller's configurable and layered architecture is independent of application logic, PHY designs, implementation tools and most importantly the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible AXI System interface makes it easy to be integrated into wide range of applications. UMMC controller leverages Mobiveil's years of experience in HyperTransport, PCI, PCle, RapidIO technologies and in creating system validated IP solutions with RTL, synthesis, simulation, board and software elements to offer lowest risk in terms of compliance and inter-operability.
- Features
- Supports multiple ranks
- Supports 16/8/4 banks per rank
- Configurable AXI address width
- Configurable Request queue depth
- Configurable Write and Read data FIFO size
- Configurable QoS through various arbitration schemes
- Supports following MC Clock to PHY Clock ratio - 1:1 (Full-rate Mode), 1:2 (Half-rate Mode), 1:4 (Quarter rate Mode)
- Supports self-refresh and partial array self-refresh
- Supports Auto-refresh, per-bank refresh and multi-bank refresh (RLDRAM)
- Supports various power down modes - Active/Precharge/Deep power down
- Supports Intelligent request scheduling
- Maximizes bus efficiency through look-ahead command processing and bank-level parallelism
Design Attributes
- Highly modular and configurable design
- Layered architecture
- Fully synchronous design
- Supports both sync and async reset
- Clearly demarked clock domains
- Software control for key features
