1 Gbps DDR rail to rail LVDS receiver
Overview
LVDS_RX is LVDS receiver with rail to rail input range. The interface to the core logic includes the output signal pins (OUTp, OUTn) to receive data and the control pins (EN_RX, EN_RES) to configure the state of the receiver. EN_RES enables the on-chip 100 Ohm resistor. The VREF12 is input voltage reference. Pin IREF_RX to get current reference from receiver bias. PAD_INp and PAD_INn are complementary input to connect to the bonding pads.
Key Features
- TSMC CMOS 0.065 um
- 2.5 V analog power supply
- 1.2 V digital power supply
- 1.2 V CMOS input and output logic signals
- 1 Gbps (DDR MODE) switching rates
- Conforms to TIA/EIA-644 LVDS standards without hysteresis
- Rail to rail input range
- Temperature range: -40 °C to + 125 °C
- Optimized for pad-limited layout design
- Portable to other technologies (upon request)
Applications
- Point-to-point data receiver
- Multidrop buses
- Clock distribution
- Backplane receiver
- Backplane data receiver
- Cable data receiver
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC CMOS 65 nm
Maturity
silicon proven
Availability
Now
TSMC
Silicon Proven:
65nm
G