650M LVDS transmitter, 5 channel
Overview
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link transmission between Host and Flat Panel Display with up to UXGA resolution. The IP converts 70-bit of CMOS/TTL data into LVDS data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin.
Key Features
- Supports 92MHz clock
- 35:5 data channel compression at data rate up to 650Mbps per channel
- Supports single pixel and dual pixel interfaces
- Converts 70 bits data to 10-pair LVDS data stream
- No external component required for PLL
- Clock edge selectable
- Compatible with TIA/EIA-644-A LVDS standard
- Power down mode
- Full industrial operating temperature range -40 ~ +85 °C
- SMIC18G Process (1.8V/3.3V)
Technical Specifications
Foundry, Node
SMIC 0.18um
SMIC
Pre-Silicon:
180nm
EEPROM
,
180nm
G
,
180nm
LL
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