IP Catalog > Analog IP > PLL IP > General Purpose PLL IP > General Purpose PLL for TSMC 180nm

General Purpose PLL for TSMC 180nm

Overview

The OT3122t180 is a flexible clock multiplier PLL function with a wide range of input and output frequencies and is designed for the TSMC 0.18µ digital, mixed signal, or high voltage CMOS processes. The design features an advanced multi-stage balanced VCO for exceptional cycle to cycle jitter performance.

This function is also available for IBM 180nm, and ams 180nm.

Key Features

  • Wide range N, M, P integer dividers.
  • 40MHz – 600MHz output frequency range.
  • Comparable frequency range 8MHz – 50MHz.
  • 18pS RMS cycle to cycle jitter at 600MHz.
  • Lock-detect function.
  • Bypass function.
  • Well defined startup behavior.
  • -40°C to 140°C temperature operation.
  • Available divider selection program.
  • Small cell area: 0.06mm2 in 0.18µ CMOS.
  • 2mW typical power dissipation.
  • 1.8V digital and analog supplies.
  • 0.18µ CMOS process compatibility.
  • Only 1.8V transistors are used in the design.
  • Silicon proven architecture.

Block Diagram

General Purpose PLL for TSMC 180nm Block Diagram

Technical Specifications

Foundry, Node
TSMC 180nm
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