The OT3122v150 is a flexible clock multiplier PLL function with a wide range of input and output frequencies and is designed for the VIS 0.15µ digital, mixed signal, or high voltage CMOS processes. The design features an advanced multi-stage balanced VCO for exceptional cycle to cycle jitter performance.
This function is also available for TSMC 130nm, TSMC 152nm, TSMC 180nm, IBM 180nm, and ams 180nm.
General Purpose PLL for VIS 150nm
Overview
Key Features
- Wide range N, M, P integer dividers.
- 40MHz – 600MHz output frequency range.
- Comparable frequency range 8MHz – 50MHz.
- 18pS RMS cycle to cycle jitter at 600MHz.
- Lock-detect function.
- Bypass function.
- Well defined startup behavior.
- -40°C to 140°C temperature operation.
- Available divider selection program.
- Small cell area: 0.06mm2 in 0.18µ CMOS.
- 1.5mW typical power dissipation.
- 1.8V digital and analog supplies.
- 0.18µ CMOS process compatibility.
- Only 1.8V transistors are used in the design.
- Silicon proven.
Block Diagram
Applications
Deliverables
- Verilog model.
- CDL netlist for LVS.
- Design review documentation.
- GDS format layout.
- Timing files.
- Integration notes.
- Production test notes.
Technical Specifications
Foundry, Node
VIS 150nm
Maturity
Silicon proven
Availability
Now
VIS
In Production:
150nm
Pre-Silicon: 150nm
Silicon Proven: 150nm
Pre-Silicon: 150nm
Silicon Proven: 150nm