Ethernet PCS 10G/25G

Overview

The Ethernet PCS 10G/25G IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 and with Clause 49 of IEEE 802.3ae specification.

The Ethernet PCS 10G/25G IP supports 10G and 25G line rates, however other Ethernet PCS speeds are available, such as 1G/2.5G and 100G.

On one side it interfaces to a SerDes device and on the application side it has a port for GMII/SGMII Ethernet signals.

The Ethernet PCS 10G/25G IP core is verified using advanced methodologies for RTL design, verification, HW verification and interoperability testing. It has been optimized for size and is a highly tested solution that will fast track any project.

Key Features

Delivers Performance
- Designed to IEEE 802.3-2018
- Supports Ethernet speeds of 10G and 25G
- Complete 10GBASE-R and 25GBASE-R PCS solution
- Can be used in any 10G or 25G Ethernet PHY application
Feature Rich
- Configurable for several operating modes and speeds
- Works with multiple SerDes widths
- IEEE Std. 802.3 Clause 46 Reconciliation Sublayer (RS) and 10 Gigabit Media Independent Interface (XGMII)
- IEEE Std. 802.3 Clause 49 Physical Coding Sublayer (PCS) for 64B 66B, type 10GBASE-R
- IEEE Std. 802.3 Clause 107 Physical Coding Sublayer (PCS) for 66B 66B, type 25GBASE-R
- IEEE Std. 802.3 Clause 45 Management Data Input/Output (MDIO) Interface
- IEEE Std. 802.3 Clause 74 Forward Error Correction (FEC) sublayer for BASE-R PHYs
- IEEE Std. 802.3 Clause 78 Energy-Efficient Ethernet (EEE)
- IEEE Std. 802.3 Clause 108 Reed-Solomon Forward Error Correction
- (RS-FEC) sublayer for 25GBASE-R PHYs
- Support XGMII for 10G and XXVGMII for 25G
- PMA/SerDes interface is default 40-bit, with 32, 64 and 66 bit being optional
- 64B 66B encoding/decoding
Highly Configurable
- Enabling use of multiple rates of Ethernet
- Easy interfacing to standard MAC’s
- Several common control bus standards are supported
- Can be delivered with integrated MAC for plug and play
- Includes test pattern Generator/Checker
Silicon Agnostic
- Designed in SystemVerilog and targeting both ASICs and FPGAs

Block Diagram

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Programming Register Specification.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Synopsys SGDC Files
- Synopsys Lint, CDC and Waivers

Technical Specifications

Maturity

Mature

Availability

Available

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