The Ultra-Low Latency 10G Ethernet MAC and PCS is the industry leading solution for latency critical Ethernet applications. The core is designed using advanced design techniques leading to unmatched ultra-low gate count utilization and amazing latency performances.
The IP core can support full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic with no dropped packets.
10-Gbps Ultra-Low Latency Ethernet MAC and PCS
Overview
Key Features
- MAC FEATURES
- Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average
- User facing logic interface 16-bit @ 644.531250MHz or 32-bit @ 322.265625MHz
- Tx Frame Check Sequence (FCS) computation and insertion
- Rx FCS error detection
- Fully compatible with Orthogone 10G TCP/UDP IP core
- PCS FEATURES
- Supports 10GBASE-R PHY based on 64B/66B encoding and scrambling
- Supports block synchronization
Block Diagram
Applications
- High Frequency Trading
- Smart NIC
- Low-Latency Switches
Deliverables
- Datasheet & user guide
- Encrypted Verilog
- Constraints file
- Reference design
- Technical support
- Optional IP design customization
Technical Specifications
Related IPs
- 10G Ultra-low latency TCP/IP + MAC + PCS IP core for FPGAs
- 10G Ultra-low latency MAC + PCS IP core for FPGAs
- Ultra-Low Latency 1G Ethernet MAC and PCS
- 25G LL MAC /PCS Ethernet IP for FPGA
- 25G Ultra Low latency, 64-bit Ethernet MAC + PCS Solution (64-bit and 128-bit UI)
- 10G Ultra Low latency, 32-bit MAC + PCS Solution (32-bit and 64-bit UI)