Ethernet MAC 10G/25G

Overview

Ethernet MAC 10G/25 IP is a solution that enables the host to communicate data using the IEEE 802.3 standard for 10G/25 speeds and is suited for use in networking equipment such as switches and routers. The Client-side inter-face for the IP is a 64 bit AXI-S and the Ethernet MAC IP comes with 64 bit XGMII interface on the PHY side.

The Ethernet MAC IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Silicon agnostic Ethernet MAC IP, suitable for ASICs and FPGAs, is pre-pared for easy integration with Ethernet PCS 10G/25 IP from Comcores.

Key Features

  • Delivers Performance
    • Designed to IEEE 802.3-2018 specification
    • Ultra low latency and compact implementation
    • Full duplex Ethernet interfaces
  • Highly Configurable
    • Can be delivered with IEEE 1588 and/or 10G/25G PCS
    • Can be delivered with statistics gathering or status vectors
    • 64-bit AXI-S64-bit AXI-Stream interface
    • Cut-through operation mode, Store and Forward is optional
    • Comes with XGMII as default PHY interface
  • Feature Rich
    • Deficit Idle Count for maximum data throughput supported
    • FCS generation supported
    • Optional statistics gathering
    • Jumbo frames support
    • Easy integration with standard AXI4-Lite control interface or APB
    • Promiscuous and non-promiscuous mode
    • Optional MDIO interface
  • Silicon Agnostic
    • Designed in SystemVerilog and targeting both ASICs and FPGAs

Block Diagram

Ethernet MAC 10G/25G Block Diagram

Deliverables

  • The IP Core can be delivered in Source code or Encrypted format.
  • The following deliverables will be provided with the IP Core license:
    • Solid documentation, including User Manual and Release Note
    • Simulation Environment, including Simple Testbed, Test case, Test Script
    • Programming Register Specification
    • Timing Constraints in Synopsys SDC format
    • Access to support system and direct support from Comcores Engineers
    • Synopsys SGDC Files
    • Synopsys Lint, CDC and Waivers

Technical Specifications

Maturity
Mature
Availability
Available
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Semiconductor IP