Ethernet MAC & PCS 10G/25G

Overview

The Ethernet MAC and PCS 10G/25G is a silicon agnostic implementation of the IEEE 802.3 standard. The Ethernet MAC IP includes the Reconsiliation Sublayer (RS), and the PCS IP comes with RS-FEC and Base-R-/FC-FEC sublayers. The IP core performs the interconnection between the Physical- and Data-link layer.

The MAC and PCS IP is a low latency cut-through implementation reaching best in market results while still keeping size at a minimum.

The core is richly featured, fully configurable and supports IEEE1588 v2.1 PTP.

Key Features

Richly Featured
- Works with multiple SerDes widths
- 64B 66B encoding/decoding
- IEEE Std. 802.3 Clause 45, 46, 49, 74, 78, 107 and 108 are supported
- (RS-FEC) sublayer for 25GBASE-R PHYs
- Can be delivered with statistics gathering or status vectors
- 64-bit AXI-S64-bit AXI-Stream interface
- Cut-through operation mode by default, Store and Forward is optional
- Deficit Idle Count for maximum data throughput
- Comprehensive statistics gathering
- Jumbo frames support with programmable MTU
- Easy integration with standard Xilinx AXI-4 Lite control interface or APB
Delivering Performance
- Designed to IEEE 802.3-2018 specification
- Low latency and compact implementation
Highly Configurable
- 10G/25G data rates with cut-through supported
- Support for IEEE 1588
Silicon Agnostic
- Designed in SystemVerilog and VHDL and targeting both ASICs and FPGAs

Block Diagram

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note
- Simulation Environment, including Simple Testbed, Test case, Test Script
- Programming Register Specification
- Timing Constraints in Synopsys SDC format
- Access to support system and direct support from Comcores Engineers
- Synopsys SGDC Files
- Synopsys Lint, CDC and Waivers

Technical Specifications

Maturity

Mature

Availability

Available

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