Ethernet PCS 1G/2.5G

Overview

Comcores PCS IP core is a silicon agnostic implementation of the PCS layer compliant with Ethernet standard IEEE 802.3-2018. The IP-core supports 1G and 2.5G line rates. The IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a Gigabit Media Independent Interface (GMII) or Serial Gigabit Media Independent Interface (SGMII). On one side it interfaces to a Serdes device and on the application side it has a port for GMII/SGMII Ethernet signals.

The IP-core is verified using advanced methodologies for RTL design, verification, HW verification and interoperability testing. It has been optimized for size and is a highly tested solution that will fast track any project.

Key Features

Richly Featured
- Configurable for several modes
- IEEE Std. 802.3 Clause 37 Auto-negotiation
- Support GMII interface for 1000BASE-X
- 8B 10B encoding to convert data to 10-bit encoded data for each lane
- Near-end loopback at both ends
Delivering Performance
- Designed to IEEE 802.3-2018 specification
- Low Latency
- Can be used in synchronous Ethernet applications
Easy to use
- AXI/APB/MDIO Slave PHY Management interface
- GMII/SGMII interfaces for attaching to Ethernet MAC
- Solid documentation
Silicon Agnostic
- Designed in VHDL and targeting both ASICs and FPGAs

Block Diagram

Applications

Any 1G/2.5G Ethernet Solution
Fits into solutions where Ethernet PCS is needed

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note
- Simulation Environment, including Simple Testbed, Test case, Test Script
- Timing Constraints in Synopsys SDC format
- Access to support system and direct support from Comcores Engineers
- Synopsys SGDC Files
- Synopsys Lint, CDC and Waivers

Technical Specifications

Maturity

Mature

Availability

Available

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