AES256-XTS IP Core

Overview

ES256-XTS IP Core (AES256XTSIP) implement the advanced encryption standard (AES) with XEX Tweakable Block Cipher with Ciphertext Stealing (XTS) which is widely used in protecting the confidentiality of data on storage devices.

AES256-XTS-STG IP implement the advanced encryption standard (AES) with XEX (XOR Encrypt XOR) tweakable block cipher which operates sequences of complete blocks and is widely used in protecting the confidentiality of data on various storage devices with interfaces such as NVMe and SATA. We also have a lineup of "2X" ideal for NVMe PCIe Gen4, and "4X", supported Gen5.

Key Features

  • Support AES-XTS mode
  • Support 256-bit key size
  • Support input data width128-bit
  • Support Ciphertext Stealing
  • Peak throughput rate at 128 Mbits/MHz
  • High-throughput, up to 51.2 Gbps @400MHz

Block Diagram

AES256-XTS IP Core Block Diagram

Technical Specifications

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Semiconductor IP