IP Catalog > Peripheral IP > DMA Controller IP > High Channel Count DMA IP Core for PCI-Express

High Channel Count DMA IP Core for PCI-Express

Overview

The High Channel Count (HCC) DMA IP core for PCI-Express is a powerful PCIe Endpoint with multiple industry standard AXI Interfaces. This IP addresses continuous streaming applications from up to 64 different data sources. Each channel is able to transmit data into a separate memory area. Up to 16 AXI Stream masters read DMA Data from the host and present it to the user logic. Additional 8 AXI4 masters are available to interface full AXI or AXI-Lite peripherals with the host.

Due to a powerful arbitration scheme, it is possible to control the priority of each DMA channel over other active channels.

All interfaces support fully parallel operation without any interferences. Interfaces that are not required can be turned off individually and do not occupy logic resources.

This IP core enables the developer to build complex PCI Express endpoints with no specific PCI Express protocol know how. The user only transmits or receives payload data and does not have to assemble valid PCI Express packets.

Key Features


  • Lowest logic resource count in the industry, fits into very small FPGA devices
    Easy timing closure for Lattice Gen3-X4
    Multi-channel architecture
    Continuous high throughput data streaming
    Non-blocking approach, an incomplete AXI Stream packet does not block other AXI Streams
    Up to 16 AXI Stream Slave interfaces with up to 64 channels addressable via TDEST
    Up to 16 AXI Stream Master interfaces
    Up to 8 AXI Masters to interface user registers
    User transmits / receives only user data without PCIe protocol knowledge
    Supports 32-Bit and 64-Bit addressing
    Independent clocking and data width for each AXI Stream interface
    Memory size up to 4 GByte per streaming channel
    Based on AMD / Altera / Lattice integrated PCISig compliant PCIe Block (HardIP)
    Link speed Gen 1-4, link widths x1-x8
    Available for most AMD, Altera and Lattice devices

Block Diagram

High Channel Count DMA IP Core for PCI-Express Block Diagram

Deliverables

  • Encrypted VHDL Source Code for easy Designflow integration
  • Comprehensive User Guide
  • Reference Design
  • Windows / Linux Driver Package (Option)
  • PCI-Express Testbench with High Speed simulation mode
  • Technical support

Technical Specifications

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High Channel Count DMA IP Core for PCI-Express
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