3D OpenGL ES 1.1 GPU IP core

D/AVE 3D is cost-efficient IP core for 3D graphics applications. This core is available for FPGAs, ASICs and SOCs, specifically designed for the embedded, automotive and infotainment market with a big emphasis on flexibility both in hardware and the software.

Architecture

The system interfaces to D/AVE 3D are very simple. In the Altera world it supports all bus interfaces available on Avalon bus architecture. In the SOC world AMBA is supported and additional bus wrappers are easy to implement with the interfaces to D/AVE 3D being very simple Master, Slave and Interrupt lines. After reset the CPU can configure or can get status information via the SBI (Slave Bus Interface) with data and memory access through the master bus interface.

To deal with unpredictable memory latency, FIFOs are added at all crucial places, which makes D/AVE 3D more performance robust. The pixel pipeline supports early Z-test. D/AVE 3D in a SOC supports multiple pixel pipelines.

Performance

All performance data given are made under the following assumptions:

• 100% cache hit rates
• No latency from external data
• Internal pipeline latency ignored
• 100 MHz.

Fillrate

The Pixel-Pipeline of the D/AVE 3D-IP can produce 1 pixel per cycle, in any configuration.

Vertex Throughput

The vertex throughput depends very much on how many light sources are enabled and if transformation is performed. It also depends on the associated vertex attributes, such as color and texture coordinates.

Triangle Throughput

The triangle throughput depends very much on the number of attributes, which have to be interpolated across the primitive.