Multi Channel DMA Flex IP Core for PCI-Express

Overview

The Multi Channel DMA IP Core for PCI-Express is a powerful PCIe Endpoint with multiple industry standard AXI Interfaces. Up to 16 independent AXI Stream Slaves write DMA Data to the Host. Up to 16 AXI Stream Masters read DMA Data from the Host and present it to the User Logic. Each channel operates on a separate memory area. Additional 8 AXI4 Masters are available to interface full AXI or AXI-Lite peripherals with the Host.
With a powerful arbitration scheme it is possible to control the priority of each DMA Channel over other active channels.
The Link Stability detector module measures the signal integrity of the PCI Express Link for lab or production tests to prevent shipments of faulty devices.
This IP Core enables the developer to build complex PCI Express endpoints with no specific PCI Express Protocol Know How. The user only transmits/receives payload data and does not have to build valid PCI Express packets.

Key Features

AXI standard interfaces for easy integration
User transmits/receives only user data without PCIe protocol
All AXI Interfaces have adjustable Datawidth and separate clocking
Vivado Blockdesigner supported
Adjustable Priority Control
Supports Scatter / Gather Memory with adjustable pagesize
Supports linear contiguous Memory as Ringbuffers
Memory Size up to 4 GByte per Streaming Channel
Performance only limited by PCI-Express Bandwidth
Based on Xilinx integrated PCI-Sig compliant PCIe Block
Link Speeds Gen1-3, Link Widths x1-x8
Available for V6, A7, K7, Zynq, V7 and Ultrascale
64 Bit or 256-Bit Architecture available

Benefits

Outstanding feature of the new version is the simultaneous transmisson of up to 16 Streaming Channels in separate memory buffers of the host system. The User can use his own clockdomain and can adjust the datawidth for each channel. The events „Start of Frame“, „End of Frame“ and „End of line“ are supported and control the storage in memory and can be used as interrupt triggers.

Block Diagram

Deliverables

Encrypted VHDL Source Code for easy Designflow integration
Comprehensive User Guide
Reference Design with DMA Performance Demo
Windows / Linux Driver Package (Option)
PCI-Express Testbench with High Speed simulation mode
Technical support

Technical Specifications

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