The Multi-Channel DMA IP Core for PCI-Express is a powerful PCIe Endpoint with multiple industry standard AXI Interfaces. Up to 16 independent AXI Stream Slaves write DMA Data to the Host. Up to 16 AXI Stream Masters read DMA Data from the Host and present it to the User Logic. Each channel operates on a separate memory area. Additional 8 AXI4 Masters are available to interface full AXI or AXI-Lite peripherals with the Host.
Due to a powerful arbitration scheme, it is possible to control the priority of each DMA channel over other active channels. The link stability detector module measures the signal integrity of the PCI Express Link for lab or production tests to prevent shipments of faulty devices.
This IP Core enables the developer to build complex PCI Express endpoints with no specific PCI Express protocol know how. The user only transmits/receives payload data and does not have to build valid PCI Express packets.
