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AES-XTS Storage Encrypt/Decrypt Engine

Overview

The AES-XTS encryption IP core implements hardware encryption/decryption for sector-based storage data. It uses the AES block cipher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths.

Two architectural versions are available to suit system size and throughput requirements. The High Throughput XTS-X is more compact and can process 128 bits/cycle independent of the key size. The Higher Throughput XTS-X2 can process 256 bits/cycle independent of the key size. Both versions have a 128-bit data path.

XTS (XEX-based Tweaked Codebook Mode with Ciphertext Stealing) is a mode of AES that has been specifically designed to encrypt fixed-size data where a possible threat has access to the stored data.

Key Features

  • Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm
  • Implemented according to the IEEE P1619™/D16 standard
  • NIST-Validated
  • Capable of processing 128 bits/cycle
  • Employs user-programmable key size of 128 or 256 bits
  • Two architectural versions:
    • The AES-XTS-X version is smaller and can process 128 bits/cycle for all key sizes
    • The AES-XTS-X2 version can process 256 bits/cycle for all key sizes
  • Arbitrary IV length
  • Easy integration & implementation
    • Works with the integrated key expansion function
    • Fully synchronous, uses only the rising clock-edge, single-clock domain, no false or multicycle timing paths, scan-ready, LINT-clean, reusable design
    • Simple input and output interface, optionally bridged to AMBA™ interfaces or integrated with a DMA engine
  • Available in VHDL or Verilog source code format, or as a targeted FPGA netlist

Block Diagram

AES-XTS Storage Encrypt/Decrypt Engine Block Diagram

Technical Specifications

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