2.4 Gbps LVDS transmitter

Overview

065TSMC_LVDS_07 is LVDS transmitter. The interface to the core logic includes differential signal pins (INP and INN) to transmit data, and control pin EN to configure the state of the transmitter. EN pin enables of the TX LVDS, OEN pin selects Hi-Z state mode in which the output is disconnected. There are other two internal pins (VREF and IREF) to get voltage reference and current reference. OUTP and OUTN are complementary outputs to connect to the bonding pads.

Key Features

TSMC CMOS 0.065 um
2.5 V analog power supply
2.5 V CMOS input logic signals
2.4 Gbps (DDR MODE) switching rates
Conforms to TIA/EIA-644 LVDS standards
Temperature range: -40 °C to + 85 °C
Optimized for pad-limited layout design
Portable to other technologies (upon request)

Block Diagram

Applications

Point-to-point data transmission
Multidrop buses
Clock distribution
Backplane data transmission
Cable data transmission
Half-duplex or duplex data transmission

Deliverables

Schematic or NetList
Abstract model (.lef and .lib files)
Layout view (optional)
Behavioral model (Verilog)
Extracted view (optional)
GDSII
DRC, LVS, antenna report
Test bench with saved configurations (optional)
Documentation

Technical Specifications

Foundry, Node

TSMC CMOS 65 nm

Maturity

Pre-silicon verification

Availability

Now

TSMC

Pre-Silicon: 65nm G

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