The LVDS transmitter converts 28-bit data into 4-pair LVDS data stream. A phase-locked transmit clock is transmitted in parallel with the data stream over the fifth LVDS channel. Every transmission cycle 28 bits of input data are sampled and transmitted. The transmitter can be programmed for either Rising-edge strobe or Falling-edge strobe through a dedicated pin. The transmitter supports Spread Spectrum Clocking type of signal input and can accurately track Spread Spectrum Clock/Data input.
SMIC 0.13um LVDS Transmitter
Overview
Key Features
- Supports 18 to 87.5MHz clock
- 28:4 data channel compression ratio at up to 612.5Mbps per channel data rate
- No special start-up sequence required between clock/data and PD inputs
- Supports Spread Spectrum Clocking, up to 100 kHz frequency modulation & deviations of ¡À2.5% center spread or -5% down spread
- Clock edge selectable
- No external component required for PLL
- Conforms to the TIA/EIA-644-A LVDS standard
- Supports power down mode. When PDN pin is logic low, the TRI-STATE output is asserted, ensuring low current dissipation in this mode
- Full industrial operating temperature range: -40 ~ +85C
- SMIC 0.13um Logic 1P8M Salicide Process (1.2V/3.3V)
- More detail, please go to below website to contact VeriSilicon location sales:http://www.verisilicon.com/cn/contactus.asp
Technical Specifications
Foundry, Node
SMIC 0.13um
SMIC
Pre-Silicon:
130nm
EEPROM
,
130nm
G
,
130nm
LL
,
130nm
LV