The OT3127 is a 128MHz output PLL function. High range M divider allows this PLL to be driven by low power non-overtone crystal oscillator circuits if required. This IP is designed for the ams amsh18 0.18µ digital or high voltage CMOS processes. Both digital and analog parts of the IP are isolated in deep N wells for noise isolation.
128MHz PLL for ams 0.18u Processes
Overview
Key Features
- Fixed N=1, and P=2 dividers.
- M integer can be set for 32 or 16.
- 128MHz output frequency.
- 15pS RMS jitter at 128MHz.
- Lock-detect function.
- Bypass function.
- Well defined startup behavior.
- -40°C to 140°C temperature operation.
- Available divider selection program.
- Small cell area: 0.04mm2 in 0.18µ CMOS.
- 1.2mW typical power dissipation.
- 1.8V digital and analog supplies.
- 0.18µ CMOS process compatibility.
- Silicon proven architecture.
Block Diagram
Technical Specifications
Foundry, Node
TSMC 130nm LP
Maturity
Silicon
Availability
Now