40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
Overview
The TRV401TSM40LP IP is a 1.1V low-power low-silicon-area AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Fractional-N Clock-PLL. It is implemented in TSMC Low-Power 40nm CMOS process technology and is especially suitable for use within wireless communication and broadcast integrated circuit RFIC or BBIC subsystems (LTE, WiFi, WiMAX, DAB, DAB+, FM, HDFM, DRM, etc).
Key Features
- Rail-to-Rail IQ ADC Input Capability
- 65dB IQ ADC SNR
- Programmable Full-Scale IQ DAC Output Current
- 65dB IQ DAC SNR
- 16MHz-to-2GHz Fractional-N PLL Output Coverage
- Independent ADC and DAC clocks + spare PLL output
- Fully-integrated 165kHz loop filter
- 13MHz to 52MHz Crystal Oscillator Reference Support
- Scalable Power Consumption
Benefits
- Low-power and low-area fully-featured 40nm AFE with robust performance and small implementation footprint.
Block Diagram
Applications
- AFE is suitable for embedding in ASIC and SoC subsystems for:
- LTE, WiFi, WiMAX, DAB, DAB+, FM, HDFM, DRM and many more
Deliverables
- Behavioural Models
- Timing Models
- GDSII Layout Database
- Netlist for LVS verification
- Usage and Integration Guidelines
- Databook
Technical Specifications
Foundry, Node
TSMC 40nm CMOS
Maturity
Contact Tetrivis
Availability
GDSII available in January 2015
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