1.68 to 1.917 GHz Phase-Locked Loop
Overview
Frequency synthesizer built on PLL by dividing the integer coefficients. Synthesizer unit includes: R-divider of external reference oscillator frequency with a programmable division factor of 1 to 31, frequency-phase detector (PFD) with the charge pump, loop filter, a voltage controlled oscillator (VCO), VCO voltage control comparators, VCO frequency divider with programmable dividing ratio of 12 to 31, VCO frequency N-divider with programmable dividing ratio of 64 to 2047, 5/6/8/10 divider, 2/4/8 divider.
Key Features
- AMS SiGe BiCMOS 0.35um
- Reference frequency from 10MHz to 125MHz
- LO1 frequency range from 1.692GHz to 1.973GHz
- LO2 frequency range from 175MHz to 225MHz
- Clock frequency range from 10MHz to 125MHz
- Charge Pump output current low imbalance
- No external components required
- Low phase noise
Applications
- Frequency clock generation
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
AMS SiGe BiCMOS 0.35um
Maturity
Silicon proven
Availability
Now