Generation of clock signal with a fixed but programmable phase difference with respect to a reference input clock is critical in many applications. An all digital DLL design with several features like wide lock range for input frequencies, short locking time, and reduced jitter is achieved by this IP.
Delay Locked Loop IP
Overview
Key Features
- Timing resolution: 80ps
- Operating frequency range: 160MHz – 700 MHz
- Lock time: 11 cycles
- Generates user configurable precise phase shifts from 00 to 3600 with a resolution of 10
- Delays multiple periodic or aperiodic signals independent of voltage and temperature.
Benefits
- The all digital nature of the DLL design allows addition of clocking resources in FPGA prototyping of new IPs and for FPGA based embedded systems using multiple clocking resources. Rigorous simulation has been carried out to evaluate the robustness and performance of the IP. The DLL can be used for a variety of applications which require precise phase shifts with respect to reference clocks to adjust for the channel routing delays on the PCB.
Block Diagram
Applications
- BIST circuits for measurement of setup and hold times
- Phase detection and tracking
- Clock recovery from input data stream
- High speed DDR type interface applications to align data with clock edges
Technical Specifications
Related IPs
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- Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 90nm 90G,GT,LP
- Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 80nm GC (CLN80GC)
- Digital Delay Locked Loop (133MHz - 333MHz) - TSMC 90nm GT (CLN90GT)
- Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 90nm GT (CLN90GT)
- Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 90nm G (CLN90G)