30-200 MHz DLL-based frequency multiplier
Overview
055TSMC_DLL_01 is a frequency multiplier that combines low phase jitter of clock signal, small area and low current consumption. Block wakes up in “pass-through” mode and passes the input signal to the output. Once configured and enabled the block waits until DLL locks and then switches output clock signal CLK_OUT to higher frequency. Disabling block switches it back into “pass-through” mode. Any mode switching is glitch-protected.
Key Features
- TSMC CMOS 55 nm
- 30 – 200 MHz output frequency
- 7.5 – 100 MHz reference frequency
- Multiplication factor 1, 2, 3 or 4
- Glitch-free mode switching
- DLL lock indication
- Easy to configure
Applications
- Digital circuit clocking
- Frequency synthesizers
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC CMOS 55 nm
Maturity
pre-silicon verification
Availability
Now
TSMC
Pre-Silicon:
55nm
FL