090TSMC_MDLL_01 is a clock multiplier accept an input clock and generates a phase-locked output clock at a multiple of the input clock frequency. As with a DLL, each rising edge of the input clock zeros the phase error of the loop. Hence this circuit combines the low phase noise of a DLL with the clock multiplication ability of a PLL. A divide-by-M counter provides a programmable multiplication ratio for the MDLL.
The block is fabricated in TSMC 90 nm CMOS Logic Process.
800/1000 MHz DLL-based frequency multiplier
Overview
Key Features
- TSMC 90 nm CMOS
- Low jitter
- Precisely aligns the clock distribution output with a reference clock
- Low current consumption
- Compact implementation of the lowpass filter
- Portable to other technologies (upon request)
Applications
- Frequency synthesizer
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC 90 nm CMOS Logic Process
Maturity
Silicon proven
TSMC
Silicon Proven:
90nm
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