IP Catalog > Analog IP > Clocking IP > Clock Synthesizer IP > ULP 10MHz Clock-Generator - GLOBALFOUNDRIES 22FDX

ULP 10MHz Clock-Generator - GLOBALFOUNDRIES 22FDX

Overview

Ultra-low power 10 MHz dock multiplier from a low frequency reference.

The Racyics® clock generator is designed to generate a 10 MHz clock from a low-frequency reference with as little power and area overhead as possible.

For highest flexibility, a wide range of reference frequencies is supported. The generated clock can be fed to the Racyics® ABX® generator.

SPECIFICATION

  • Supply Voltages [V]: 0.80
  • ZBB (Zero Bias): yes

Key Features

  • The All Digital Frequency Locked Loop (ADFLL) architecture is reduced to the minimum amount of hardware necessary to generate a 10 MHz clock
  • High energy efficiency: Only 5 μW are consumed during operation
  • A reference clock divider allows reference clock frequencies from 32 kHz to 1 MHz

Block Diagram

ULP 10MHz Clock-Generator - GLOBALFOUNDRIES 22FDX Block Diagram

Deliverables

  • Verilog simulation models
  • .lib/.db timing and power models (NLDM)
  • .lef layout abstract views
  • NDM and Milkyway libraries
  • GDSII files
  • LVS netlist

Technical Specifications

Short description
ULP 10MHz Clock-Generator - GLOBALFOUNDRIES 22FDX
Vendor
Vendor Name
Foundry, Node
GLOBALFOUNDRIES 22FDX
Maturity
silicon-proven
GLOBALFOUNDRIES
Pre-Silicon: 22nm FDX
Silicon Proven: 22nm FDX
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