Very Low Area Fractional-N Frequency Synthesizer PLL

Overview

Key Features

• Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
• Input & output frequency ranges greater than 1000:1
• Program while running to optimize for lowest jitter or lowest power
• Automatically adjusts for any input frequency, so no complicated programming is required
• 24 bit fractional resolution so output frequency is programmable in steps less than 0.01ppm
• Noise Cancellation DAC enables ultra-low jitter in fractional mode -- better than "Low jitter" integer PLLs from many others
• Small footprint
• Built-in supply decoupling. No external components required
• Low area on chip -- keepouts = 0 in many cases
• Optional Spread Spectrum clock generation capability

Benefits

• Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
• PLL can be programmed while running to optimize for lowest jitter or lowest power - Programmable to use less than 1mW for less demanding clocks, yet can also be programmed to generate a PCIe1/2/3 compliant spread-spectrum reference clock or DDR 6400 reference.
• Low area on chip -- keepouts = DRC limit in most cases
• No external components required
• No additional supply decoupling required
• Self biased and automatically adjusts for any input frequency, so no complicated programming is required

Deliverables

• GDSII
• CDL Netlist (MG Calibre Compatible)
• Functional Verilog Model
• Liberty timing models (.lib)
• LEF
• Application Note

Technical Specifications