We Need ''Enterprise'' System-Level Solutions
(11/20/2006 9:43 AM EST), EE Times
This is the first of a two part series. The second article will appear shortly.
To close the gaps in systems development across distributed design and verification teams it will become necessary to plan, design, and verify embedded software closer in-line with the way we currently design and verify hardware. In the past, embedded software development, or more specifically verification, has taken a back seat when compared to the hardware. In other words, as long as the perception remains that software can be relatively "easily" changed and firmware updates and patches can be made available, it will not be given the same level of focus, overall planning, or effort as the hardware.
This oversight or lack of planning in the area of hardware-software co-development has resulted in a situation where less investment and methodology development are budgeted for comprehensive "Enterprise" System-Level solutions. The increasing number of consumer products with embedded processors and embedded software, combined with time-to-market and system-level quality pressures, forced many system companies to re-think their design and verification strategy. The main area being overlooked includes hardware and software verification methods and tools that work together in a much more efficient, measured and managed way.
In order to make this leap into the world of hardware-software co-verification at the system level, companies will require new ways of thinking holistically. They will need to manage the various technologies, engines, verification IP, and methodologies for multi-specialist teams across the entire project (hardware and software). This broader awareness will address serious product lifecycle concerns and market pressures for those developing advanced SoCs and systems, which will in turn open up opportunities for EDA companies developing innovative enterprise-wide, system-level solutions.
To read the full article, click here
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related White Papers
- IP Verification : SoC/IP designs need next-gen solutions for integration verification
- ''Enterprise'' System Level (ESL) Verification -- PART II
- Why we need an analog design flow that's like digital now
- Accurate System Level Power Estimation through Fast Gate-Level Power Characterization
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS