The Need for Variable Precision DSP Architecture
By Suhel Dhanani, Altera Corp.
Programmable Logic DesignLine (05/05/10, 02:57:00 AM EDT)
Two fundamental trends driving the electronic infrastructure business are the need for higher data (and increasingly mobile) bandwidth and the need for higher resolution video. While somewhat distinct, these trends are overlapping in that video is the primary driver for the ever-increasing data bandwidth requirements. Cisco estimates that �all forms of video will account for close to 90% of consumer (Internet) traffic by 2012�.�
The need for increased data bandwidth inherently implies higher performance and higher precision data processing. More and higher resolution data needs to be processed, while maintaining stringent power and cost specifications. Conceptually Figure 1 shows that while processing performance/precision needs are going up�total system cost and power targets remain the same.

Figure 1. Increasing Processing with Strict Power and Cost Budgets
Video processing provides a very compelling case study of this trend. We have seen the video infrastructure gearing up to handle the processing of high definition (HD) video (up from standard definition or SD) and now even 4K (3D) video resolutions. As this transition takes place�the number of pixels that need to be processed per frame as well as the color depth (the pixel resolution) increases, thus enabling higher image quality.
To read the full article, click here
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- NoC Verification IP
- Simulation VIP for Ethernet UEC
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
Related Articles
- Reusable architecture is DSP framework
- Understanding the reuse of a DSP architecture for different designs (Ceva)
- Embedded DSP Software Design Using Multicore a System-on-a-Chip (SoC) Architecture: Part 2
- A MAC-less Neural Inference Processor Supporting Compressed, Variable Precision Weights
Latest Articles
- Analog Foundation Models
- Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators
- RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
- Exclude Smart in Functional Coverage
- A 0.32 mm² 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection