Using simulation and emulation together to create complex SoCs
Laurent Ducousso, STMicroelectronics NV
EETimes (3/23/2011 9:06 AM EDT )
Two trends are conspiring to make complex modern chip development more and more difficult: the increasing amount of software content required for what are essentially monolithic embedded systems, and ever-shortening market windows, especially for consumer-oriented products. Writing more software in less time is a tall order; the most straightforward way to get things out earlier is to start writing sooner. But until you can test an overall system, including the software, there’s only so much you can do.
At STMicroelectronics, we find ourselves increasingly using emulation as an important tool for testing complex SoCs with lots of software content. But this only really works as part of an integrated process that starts at the architectural modeling stage and proceeds all the way through the final implementation of hardware.
We make chips that address various wall-plugged consumer applications, notably set-top boxes and digital TV. As such, we work in a world of rapidly changing technology and consumer expectations – the actual product life can easily be shorter than the time it takes to develop the chip. Mistakes and delays can kill an entire project – and with the cost of such projects these days, wasting that kind of expense is something even a large company like us can ill afford.
So we have invested in a process that attempts to minimize rework, focusing instead on gradual refinement of early models into working silicon. The process provides an example of how TLM technology, virtual platforms, and a good emulator make this possible.
To read the full article, click here
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related White Papers
- SystemC Verification, Simulation & Emulation of Secure Digital IP
- An Efficient Device for Forward Collision Warning Using Low Cost Stereo Camera & Embedded SoC
- A cost-effective and highly productive Framework for IP Integration in SoC using pre-defined language sensitive Editors (LSE) templates and effectively using System Verilog Interfaces
- Safety Verification and Optimization of Automotive Ethernet Using Dedicated SoC FIT Rates
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS