Using FPGAs to build a compact, low cost, and low power Ethernet-to-Network Processor bridge
By Ted Marena, Lattice Semiconductor
Jul 11 2007 (12:49 PM), Embedded.com
As carriers and cable providers begin rolling out triple-play and VoD services to their customers, OEMs are increasing their development efforts to roll out IP- (Internet Protocol) based systems, including PONs, CMTS, IP DSLAMs and other access and last-mile equipment. The common underlying physical layer for this is the ubiquitous Ethernet technology, now coupled with sophisticated QoS (Quality of Service) overlays.
Within this context, design engineers are devoting more design effort to connect their switched Ethernet backplanes to the system line cards and, specifically, to their Network Processors. System architects often select Ethernet Switches and Network Processors based on their individual features and rarely consider the challenge of interconnecting the two.
Design engineers are then left with the challenge of developing the bridge, fitting the solution and implementing it cost effectively. Moreover, because both interfaces run at very high speeds, power is also a significant concern. All of these challenges are addressed in this article.
Related Semiconductor IP
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
- UCIe RX Interface
Related Articles
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power
- BCD Technology: A Unified Approach to Analog, Digital, and Power Design
- Build low power video SoCs with programmable multi-core video processor IP
Latest Articles
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS
- A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA