Using a memory management unit
Colin Walls, Mentor Graphics
embedded.com (February 09, 2014)
Memory management units (MMUs) are incorporated in, or available for, a wide range of embedded CPUs. Under some circumstances their use is mandatory; in other situations they might represent an unwanted overhead. This article looks at what MMUs do and how they might be applied. Process and thread models for multi-tasking are compared and contrasted, and an intermediate option is considered that might provide a compromise between security and performance requirements.
Physical and logical addresses
When you first start learning how to program, the concept of an address is unimportant, as high level languages insulate the programmer from such nastiness. It is only when a developer wants to understand or write assembly language or really appreciate what is happening with pointers that addresses become a concern.
Every byte of memory has a unique address. Actually that is not quite true, as some processor architectures utilize multiple address spaces, but ultimately every byte may be specified uniquely in some way. Commonly, a system has a single area of memory with a starting address of zero. This is not a firm rule, as the memory architecture could be set up such that the address space starts at some other value. Other systems have multiple areas of memory that may not be contiguous – maybe the program and data memory are separate, for example.
To read the full article, click here
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Digital PUF IP
Related White Papers
- Advanced Power Management in Embedded Memory Subsystems
- Using non-volatile memory IP in system on chip designs
- Performance optimization using smart memory controllers, Part 1
- Metric Driven Verification of Reconfigurable Memory Controller IPs Using UVM Methodology for Improved Verification Effectiveness and Reusability
Latest White Papers
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
- How Mature-Technology ASICs Can Give You the Edge
- Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY