Tested and effective methods for speeding up DSP algorithms

Many electronics and digital products use digital signal processing (DSP) algorithms in them. Before any algorithm gets into the product, an optimization process is applied to it. The optimization process ensures that the algorithm uses the least possible resources from the system, while delivering the performance the design requires. The optimization is performed to save memory space, clock cycles, and power levels.

Reducing the required memory means shrinking the algorithm foot-print, and reducing the cycle consumption means speeding the algorithm. In most cases power savings have resulted with just these two kinds of optimizations.

But understanding algorithm, processor architecture, compiler and fine 'C' and assembly language practice is required to efficiently optimize an algorithm. Since early days, assembly coding has been used to achieve these goals.

But with the availability of powerful 'C' compliers it is now possible for most embedded programmers to successfully perform both source and algorithm level optimization if they follow some basic tested and effective guidelines.

This article describes the optimization process basics and various practical 'C' level skills needed to accelerate an algorithm. Processor and complier specific options are excluded as they are typically found in the respective vendor documents.

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