Leveraging system models for RTL functional verification
Jerome Bortolami, Calypto Design Systems
(12/03/2007 9:00 AM EST), EE Times
Sequential logic equivalence checking provides an edge
Register transfer level (RTL) verification remains the bottleneck in digital hardware design. Industry surveys show that functional verification accounts for 70 percent of the total design effort. Yet, despite the emphasis on verification, more than 60 percent of all design tapeouts require a respin. The predominant cause is logic or functional flaws, defects that could have been caught by functional verification. Clearly, improved verification techniques are needed.
Design teams commonly use system models for verification. System models have advantages over RTL for verification: namely, ease of development and run-time performance. The challenge is bridging the gap between system-level verification and creating functionally correct RTL. A methodology known as sequential logic equivalence checking has the ability to bridge this gap by formally verifying RTL implementations against a specification written in C/C++ or SystemC.
This case study describes the system-level to RTL design and verification flow of a commercial graphics processing chip. In this flow, system models were developed to validate the arithmetic computation of video instructions and were then used to verify the RTL implementation using sequential logic equivalence checking.
(12/03/2007 9:00 AM EST), EE Times
Sequential logic equivalence checking provides an edge
Register transfer level (RTL) verification remains the bottleneck in digital hardware design. Industry surveys show that functional verification accounts for 70 percent of the total design effort. Yet, despite the emphasis on verification, more than 60 percent of all design tapeouts require a respin. The predominant cause is logic or functional flaws, defects that could have been caught by functional verification. Clearly, improved verification techniques are needed.
Design teams commonly use system models for verification. System models have advantages over RTL for verification: namely, ease of development and run-time performance. The challenge is bridging the gap between system-level verification and creating functionally correct RTL. A methodology known as sequential logic equivalence checking has the ability to bridge this gap by formally verifying RTL implementations against a specification written in C/C++ or SystemC.
This case study describes the system-level to RTL design and verification flow of a commercial graphics processing chip. In this flow, system models were developed to validate the arithmetic computation of video instructions and were then used to verify the RTL implementation using sequential logic equivalence checking.
To read the full article, click here
Related Semiconductor IP
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
Related Articles
- RTL Prototyping Brings Hardware Speeds to Functional Verification
- Verifying large models in RTL simulation
- Sequential equivalence checking for RTL models
- Timing Annotation of UnTimed Functional Models for Architecture Use-Case
Latest Articles
- VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems
- A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators
- Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks