PowerSoC solves switch-mode DCDC noise and space issues
Michael Laflin, Enpirion, and Austin Lesea, Xilinx
EETimes (2/5/2012 5:00 PM EST)
Introduction
Conversion efficiency is driving FPGA system designers away from the use of linear regulators and toward the use of switch mode DCDC converters. While switch-mode DCDCs offer dramatic increases in efficiency, they also require a much more complex design, increase part count and footprint, and most significantly for high-speed IO, switch-mode DCDC converters are a source of noise.
This article describes the various components of noise in a switch-mode DCDC converter and demonstrates how PowerSoCs can minimize those components. The article further shows design examples and demonstrates how PowerSoCs can power high speed IO with performance equivalent to or better than Linear Regulators.
To read the full article, click here
Related Semiconductor IP
- Nano power DC-DC converter with ultra-low quiescent current and high efficiency at light load in TSMC 40uLPeF
- 3.3 - 4.2V to -3.7V step-down DC/DC converter
- 3.3 - 4.2V to 0 - minus 200V step-down DC/DC converter
- 3.3 - 4.2V to 0 - 200V step-up DC/DC converter
- 3.3 - 4.2V to 0 - minus 100V step-down DC/DC converter
Related Articles
- How to simplify switch-mode DC-DC converter design
- Guide to Choosing the Best DCDC Converter for Your Application
- Understanding Efficiency of Switched Capacitor DC-DC Converters for Battery-Powered Applications
- LVDS ups A/D converter data rates
Latest Articles
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
- In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events