Power-aware FPGA design (Part 1)

By Hichem Belhadj, Vishal Aggrawal, Ajay Pradhan, and Amal Zerrouki, Actel
Programmable Logic DesignLine (02/04/09, 12:22:00 PM EST)

Abstract
Power consumption requirements in new autonomous, multimedia-savvy consumer products that can store, transmit, and receive data have catapulted system architects and board and chip designers into a new realm. Even when designers attempted to reduce system power consumption, their approaches were not comprehensive and focused enough to achieve optimal results.

This two-part article covers several aspects of FPGA power consumption: FPGA architecture and features, the power components associated with FPGAs, and the FPGA process technology development itself. It also provides a new look at power dissipation numbers, and questions the traditional methods of estimating and measuring power. We show that design and system power profiles are keys to successfully reducing power consumption.

Introduction
The latest process technologies revealed a troublesome issue: the dramatic increase in static power. This issue is worse for FPGAs than for ASICs. Today, power comes to play in bill-of-materials (BOM), board design, chip design, testing, and production flow.

ASIC and ASSP vendors dealt with power in various ways; however, FPGA vendors have only recently introduced novel and power-friendly FPGA architectures and features. A key feature is the availability of various power modes and power voltages. For example, Actel IGLOO and ProASIC3L FPGA families feature various power modes with state saving (On, Static, Idle, and Flash*Freeze modes), as well as operation at 1.5 V or 1.2 V for both the core and the I/Os.

Similarly, Altera announced a more power-friendly derivative family of the Max' II, called Max IIZ [MaxIIZ2007]. Xilinx led the charge in 2006 with the CoolRunner CPLD families [CoolRunner2006], and now offers power derivatives of its Virtex families.

All three vendors provide several analysis tools to help users estimate the power consumption at different stages of their design cycles [BADAZ2008]. Efforts to improve the backend tools also help reduce wasted power [Libero2009]. This article aids power reduction by clearly defining and describing FPGA design techniques and their impact on power and energy consumption.

The goal of this article is to examine each design step and each component of system power with the purpose of providing techniques to reduce wasteful power consumption. These techniques cover system partitioning, chip design, and board layout. Chip design includes RTL coding, DesignWare arithmetic architecture power profiling, and place-and-route hints.

Some of these techniques may initially seem "old hat," but they have been revisited to fit the profile of applications required by most of the new consumer products targeting low-power FPGAs. In addition, available power modes are exploited to minimize further power consumption, energy, and battery life.

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