Parametric yield: Do you know what you miss?
Yoann Courant, Firas Mohamed, Infiniscale
EETimes (11/10/2010 1:06 AM EST)
Since moving to sub 65-nanometer technologies, Pre-Defined Corners (PDC) verification has attained its limits. The number of corners to verify has become huge with always the possibility of over-design. The worst is that these corners cannot guarantee the design. Some corners could fall inside the process parameters space while others do not really need to be tested.
In this context, EDA has started looking for solutions for this new and key concern. Many solutions have been developed on the back-end side to reduce variability, analyze yield or enhance it. These solutions, although very useful, were not sufficient. Another effort at design level has been made concerning parametric yield. This is thoroughly developed in this paper.
Today, the EDA market offers tools based on the following different approaches:
- Manual sizing and PDC
- Manual sizing and simulator-based analysis
- Simulator-based sizing and yield optimization
- Model-based sizing and yield optimization
To read the full article, click here
Related Semiconductor IP
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
Related White Papers
- MEMS -> D-MEMS yield new flexibility for optical nets
- SoCs optimized for power yield better performance
- 1T-SRAM improves yield, benefits SoCs
- BIST, BISR tools push up quality, yield
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design