Optimize SoC Design with a Network-on-Chip Strategy
By Andy Nightingale, Arteris
Utilizing physically aware interconnect IP from trusted third-party vendors can reduce design time and increase productivity.
Today’s system-on-chip (SoC) devices can contain hundreds of millions to over a hundred billion transistors, depending on the application. The only way to create designs of this complexity is to employ large numbers of functional blocks called intellectual-property (IP) blocks or IPs.
Many of these blocks embody well-known and standard functions, such as processor cores, communication cores (Ethernet, USB, I2C, SPI, etc.) and peripheral processes. Rather than spend valuable time and resources re-implementing these functions from scratch, SoC design teams acquire these IPs from respected third-party vendors.
Access to robust, tested, and proven IP speeds up the development process and reduces risk. Using third-party IP for common functions frees the SoC design team to focus on their own “secret sauce” IP blocks, which will differentiate their SoC from competitive offerings.
To read the full article, click here
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Digital PUF IP
Related White Papers
- SoC design: When is a network-on-chip (NoC) not enough?
- SoC design: When a network-on-chip meets cache coherency
- VLSI Physical Design Methodology for ASIC Development with a Flavor of IP Hardening
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
Latest White Papers
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
- How Mature-Technology ASICs Can Give You the Edge
- Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY