Optimize SoC Design with a Network-on-Chip Strategy
By Andy Nightingale, Arteris
Utilizing physically aware interconnect IP from trusted third-party vendors can reduce design time and increase productivity.
Today’s system-on-chip (SoC) devices can contain hundreds of millions to over a hundred billion transistors, depending on the application. The only way to create designs of this complexity is to employ large numbers of functional blocks called intellectual-property (IP) blocks or IPs.
Many of these blocks embody well-known and standard functions, such as processor cores, communication cores (Ethernet, USB, I2C, SPI, etc.) and peripheral processes. Rather than spend valuable time and resources re-implementing these functions from scratch, SoC design teams acquire these IPs from respected third-party vendors.
Access to robust, tested, and proven IP speeds up the development process and reduces risk. Using third-party IP for common functions frees the SoC design team to focus on their own “secret sauce” IP blocks, which will differentiate their SoC from competitive offerings.
To read the full article, click here
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- NoC Verification IP
- Simulation VIP for Ethernet UEC
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
Related Articles
- SoC design: When is a network-on-chip (NoC) not enough?
- SoC design: When a network-on-chip meets cache coherency
- A logically correct SoC design isn’t an optimized design
- VLSI Physical Design Methodology for ASIC Development with a Flavor of IP Hardening
Latest Articles
- Analog Foundation Models
- Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators
- RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
- Exclude Smart in Functional Coverage
- A 0.32 mm² 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection