New Ethernet Adaptation Layer Adds Control Option to MIPI A-PHY Automotive Networks
By Sharmion Kerley, MIPI Director of Marketing and Membership
To satisfy the demand for both advanced safety features and better driver and passenger experiences, automakers are adding more displays, larger in size and with greater resolutions, to the digital cockpit. This trend has created a need for more in-vehicle wiring, which in turn adds cost, weight and complexity to new car designs.
This is one of the many challenges being addressed by the introduction of MIPI Automotive SerDes Solutions, or MASS for short, which offers a standardized framework for integrating cameras and displays with their associated electronic control units (ECUs) using the MIPI A-PHYSM asymmetric SerDes physical layer as its foundation.
The most recent addition to the MASS framework is MIPI PALSM/ETH v1.0, an A-PHY protocol adaptation layer (PAL) released in March 2022 that lets OEMs and Tier 1 suppliers use a single A-PHY cable for both high-speed image data and low-speed Ethernet control data between automotive display modules and their ECUs.
To read the full article, click here
Related Semiconductor IP
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
Related Articles
- A Look at New Open Standards to Improve Reliability and Redundancy of Automotive Ethernet
- New Developments in MIPI's High-Speed Automotive Sensor Connectivity Framework
- Common physical layer issues underlie new I/O standards
- e Verification Environment for FlexRay Advanced Automotive Networks
Latest Articles
- VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems
- A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators
- Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks