Multiple clock domain SoCs: Verification techniques
Tejas Dave, Amit Jain & Divyanshu Jain (eInfochips)
EDN (October 23, 2014)
With technology advancement and introduction of more complex SOCs, data transfer between multiple clock domains is more frequent and demanding, and CDC design and verification becomes a more challenging task. An understanding of metastability plays a key role in understanding CDC problems and associated design challenges. Adoption of new verification techniques in the early stages also plays an important role in easing and speeding up multi-clock domain design and verification activities.
EDA tool vendors provide various solutions to check whether proper implementation of CDC is done or not. EDA vendors like Synopsys, Atrenta, Mentor, and Cadence provide solutions through simulation, Linting, and LEC. Here are some of our experiences:
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
- Parameterizable compact BCH codec
Related Articles
- Optimizing clock tree distribution in SoCs with multiple clock sinks
- An Automated Flow for Reset Connectivity Checks in Complex SoCs having Multiple Power Domains
- Clock domain modeling is essential in high density SoC design
- Techniques to make clock switching glitch free
Latest Articles
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension