Multiple clock domain SoCs: Verification techniques
Tejas Dave, Amit Jain & Divyanshu Jain (eInfochips)
EDN (October 23, 2014)
With technology advancement and introduction of more complex SOCs, data transfer between multiple clock domains is more frequent and demanding, and CDC design and verification becomes a more challenging task. An understanding of metastability plays a key role in understanding CDC problems and associated design challenges. Adoption of new verification techniques in the early stages also plays an important role in easing and speeding up multi-clock domain design and verification activities.
EDA tool vendors provide various solutions to check whether proper implementation of CDC is done or not. EDA vendors like Synopsys, Atrenta, Mentor, and Cadence provide solutions through simulation, Linting, and LEC. Here are some of our experiences:
To read the full article, click here
Related Semiconductor IP
- RVA23, Multi-cluster, Hypervisor and Android
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- H.264 Decoder
Related White Papers
- Optimizing clock tree distribution in SoCs with multiple clock sinks
- An Automated Flow for Reset Connectivity Checks in Complex SoCs having Multiple Power Domains
- Clock domain modeling is essential in high density SoC design
- Techniques to make clock switching glitch free
Latest White Papers
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design