Multiple clock domain SoCs: Verification techniques
Tejas Dave, Amit Jain & Divyanshu Jain (eInfochips)
EDN (October 23, 2014)
With technology advancement and introduction of more complex SOCs, data transfer between multiple clock domains is more frequent and demanding, and CDC design and verification becomes a more challenging task. An understanding of metastability plays a key role in understanding CDC problems and associated design challenges. Adoption of new verification techniques in the early stages also plays an important role in easing and speeding up multi-clock domain design and verification activities.
EDA tool vendors provide various solutions to check whether proper implementation of CDC is done or not. EDA vendors like Synopsys, Atrenta, Mentor, and Cadence provide solutions through simulation, Linting, and LEC. Here are some of our experiences:
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related White Papers
- Optimizing clock tree distribution in SoCs with multiple clock sinks
- An Automated Flow for Reset Connectivity Checks in Complex SoCs having Multiple Power Domains
- Clock domain modeling is essential in high density SoC design
- Techniques to make clock switching glitch free
Latest White Papers
- RISC-V basics: The truth about custom extensions
- Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
- Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
- relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions