Multimedia display development for automotive and industrial apps speeded by FPGA-plus-IP platform
By Davor Kovacec, CEO, Xylon
March 15, 2008 -- videsignline.com
With ever-shrinking time-to-market windows for multimedia applications, design tools and pre-designed IP blocks can be important elements for quickening the design process. The right development platform can help designers in the balancing act between the contradictory requirements of having a standard but still highly configurable solution.
Combining Xilinx FPGAs with the Xylon logicBRICKS IP cores library, the logiCRAFT 3 compact multimedia display development platform lets you quickly turn system designs running on this generic FPGA development platform into specialized products.

Figure 1: LogiCRAFT 3 compact multimedia display development platform
This design approach enables a large portion of design reuse through different hardware (IP cores) and software modules. You can reuse these same modules in many system designs for different applications.
March 15, 2008 -- videsignline.com
With ever-shrinking time-to-market windows for multimedia applications, design tools and pre-designed IP blocks can be important elements for quickening the design process. The right development platform can help designers in the balancing act between the contradictory requirements of having a standard but still highly configurable solution.
Combining Xilinx FPGAs with the Xylon logicBRICKS IP cores library, the logiCRAFT 3 compact multimedia display development platform lets you quickly turn system designs running on this generic FPGA development platform into specialized products.

Figure 1: LogiCRAFT 3 compact multimedia display development platform
This design approach enables a large portion of design reuse through different hardware (IP cores) and software modules. You can reuse these same modules in many system designs for different applications.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related Articles
- MPEG Standards -> MPEG-7 tackles multimedia content
- MPEG Standards -> Metadata captures multimedia diversity
- MPEG Standards -> End user reaps benefit of wireless multimedia structure
- Streaming multimedia challenges DSP design
Latest Articles
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension