How effective use of ESL tools can increase your HW/SW system design productivity
(10/05/07, 12:15:00 AM EDT) -- Embedded.com
For several years, the semiconductor industry has not been driven by a single killer application, but by the convergence and consumerization of existing markets. Moreover, the increased complexity that comes with 90nm and smaller geometries has made product development harder and more costly.
The net result for engineers is a myriad of severe challenges, including hardware/ software (HW/SW) co-design, power management and verification. An Electronic System Level (ESL) methodology offers a viable solution to these challenges if it includes a clear-cut path to established implementation flows.
ESL, which is defined here as design and verification done above the RTL, is used today by most semiconductor and system companies. For years, architects have been writing ESL models to prototype and validate systems.
In the past, however, other engineers seldom used these models. What has changed is that ESL languages, tools and methodologies now exist, which fosters reuse and allows the ESL investment to be leveraged across the design process.
Figure 1: Separation of computation and communication allows for reuse across verification.
To read the full article, click here
Related Semiconductor IP
- EMFI Detector
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
Related White Papers
- How to use FPGAs to develop an intelligent solar tracking system
- How to use the CORDIC algorithm in your FPGA design
- How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity
- How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power
Latest White Papers
- On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions