Get multicore performance from one core
Apr 18 2007 (0:15 AM), Embedded Systems Design
System-on-chip (SoC) designers know what it's like to do more with less. They're constantly challenged by ever-increasing constraints on system cost and power consumption while being tasked with increasing the performance and functionality of their designs. The tricks of the trade available to designers are, at best, a set of difficult trade-offs.
For example, some designers ramp up the processor's clock speed, but this approach usually results in higher power consumption. In addition, memory performance hasn't kept pace with processor technology, as Figure 1 illustrates, and this mismatch limits any significant gains in system performance. A multicore system is another option, but this suffers from a larger die area and higher cost. Any performance increase comes at a fairly substantial cost in silicon and system power.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related White Papers
- How to get the best performance and utilization from Xilinx Virtex-5 FPGAs
- Achieving multicore performance in a single core SoC design using a multi-threaded virtual multiprocessor: Part 2
- A Flexible, Low Power, High Performance DSP IP Core for Programmable Systems-on-Chip
- Putting multicore processing in context: Part One
Latest White Papers
- Morphlux: Programmable chip-to-chip photonic fabrics in multi-accelerator servers for ML
- RISC-V basics: The truth about custom extensions
- Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
- Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
- relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication