Formal property verification: A tale of two methods
David Vincenzoni, STMicroelectronics
EDN (January 15, 2018)
The Formal Property Verification (FPV) methodology often gets used in the last step of verification flow, after much time spent building a complex random constrained UVM (Universal Verification Methodology) environment where some corner cases are still not covered.
Other times, FPV is used when a silicon bug is found that was not raised during the dynamic verification phase.
In a wisely applied verification flow, FPV should be used in the first phase, as soon as the RTL (Register Transfer Logic) code is available.
Here we look at two examples of verification flow:
- A digital block verified through a UVM test bench
- Then, first verified using FPV flow.
To read the full article, click here
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Digital PUF IP
Related White Papers
- Don't over-constrain in formal property verification (FPV) flows
- Formal, simulation, and AMBA verification IP combine to verify configurable powerline networking SoC
- How formal verification saves time in digital IP design
- Formal Verification Has It Covered!
Latest White Papers
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
- How Mature-Technology ASICs Can Give You the Edge
- Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY