Why FIR sensing technology is essential for achieving fully autonomous vehicles
Yakov Shaharabani, AdaSky
embedded.com (June 12, 2018)
The automotive industry is experiencing an influx of new technology as it never has before. Automakers are promising to deploy fully autonomous vehicles on public roads within the next few years and are predicting that mass market adoption will not be far behind. But while top-tier automakers and tech companies are eager to accelerate these autonomous innovations, achieving full vehicle autonomy will require a sensing technology that enable cars to “see” the world around them and react better than human drivers.
Current sensing technologies, like LiDAR, radar, and cameras, have perception problems that require a human driver to be ready to take control of the car at any moment. For this reason, the role of sensors has only intensified; to achieve Level 3-5 autonomous driving, vehicles need sensors both in greater quantity and of greater ability. This article explores the sensing capabilities of current solutions, such as radar and LiDAR (light detection and ranging), and why FIR (far-infrared) in a fusion solution is ultimately the key to achieving Level-3, 4, and 5 autonomous driving.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- eFuse Controller IP
- Secure Storage Solution for OTP IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
Related Articles
- Inside the Xilinx Kintex-7 FPGA: A closer look at the first FPGA to use HKMG technology
- A Platform-Based Technology for Fault-Robust SoC Design
- A Platform-Based Technology for Fault-Robust SoC Design
- How to write an optimized FIR filter
Latest Articles
- Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference
- Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor