It's Time to Look at FD-SOI (Again)
By Eric Hong, Mixel and Nik Jedrzejewski, NXP
EETimes (January 21, 2021)
The emergence of FD-SOI, (fully depleted silicon-on-insulator) and its subsequent maturity over the years, has made it one of the seminal process advancements for low power semiconductor design. Although not as prevalent as the mainstream bulk CMOS process, FD-SOI has provided an important set of benefits to semiconductor product designers. These advances intersect with market demands for devices with more intelligence and better connectivity.
Envisioning and developing these new products require the support of an entire ecosystem. It is important to appreciate the investment necessary to build an ecosystem to support a process like FD-SOI. Although the choice of foundry, process technology, or silicon IP is not a concern of the consumer using such devices, it is of critical concern to those of us who need to build these products.
What differentiates FD-SOI as an important process technology? There are a set of intrinsic benefits in comparison with bulk silicon, including improved power, performance, and area metrics. There are also specific operational optimizations that improve both the power and performance of FD-SOI devices.
To read the full article, click here
Related Semiconductor IP
- Samsung 28nm FDSOI 1.8v/1.0v LVDS Transmitter
- General Purpose Temperature Sensor - 2°C accuracy – 10-bit Digital Readout - Globalfoundries 22nm FD-SOI
- USB3.0 PHY on GF22FDX and Samsung 28nm FDSOI
- GLOBALFOUNDRIES 22nm FDSOI USB3.0 PHY
- Adaptive Body-Bias Subsystem enabling Process, Voltage & Temperature compensation to leverage FDSOI body-biasing capabilities
Related White Papers
- Electronic Circuit Design for RF Energy Harvesting using 28nm FD-SOI Technology
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- How NoC architecture solves MCU design challenges
- Not all overvoltage tolerant GPIOs are the same
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design