A brief primer on embedded SoC packaging options
Deepak Behera, Sumit Varshney, Sunaina Srivastava, and Swapnil Tiwari, Freescale Semiconductor
11/20/2011 9:16 PM EST
With shrinking technology, voltage levels are being reduced, lowering noise margins required to enable a clean design from a signal integrity perspective. Higher operating frequency requirements further complicate design closure. Semiconductor packages are a quintessential piece of the signal integrity puzzle.
This article addresses the basics of packaging such as types of packages and their advantages and disadvantages, future trends, and factors to be considered while choosing a package.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
- Parameterizable compact BCH codec
Related Articles
- An Efficient Device for Forward Collision Warning Using Low Cost Stereo Camera & Embedded SoC
- Testing Of Repairable Embedded Memories in SoC: Approach and Challenges
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 1
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 2
Latest Articles
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension