A brief primer on embedded SoC packaging options
Deepak Behera, Sumit Varshney, Sunaina Srivastava, and Swapnil Tiwari, Freescale Semiconductor
11/20/2011 9:16 PM EST
With shrinking technology, voltage levels are being reduced, lowering noise margins required to enable a clean design from a signal integrity perspective. Higher operating frequency requirements further complicate design closure. Semiconductor packages are a quintessential piece of the signal integrity puzzle.
This article addresses the basics of packaging such as types of packages and their advantages and disadvantages, future trends, and factors to be considered while choosing a package.
To read the full article, click here
Related Semiconductor IP
- Multi-channel Ultra Ethernet TSS Transform Engine
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
- HiFi iQ DSP
- CXL 4 Verification IP
Related Articles
- An Efficient Device for Forward Collision Warning Using Low Cost Stereo Camera & Embedded SoC
- Testing Of Repairable Embedded Memories in SoC: Approach and Challenges
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 1
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 2
Latest Articles
- GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon
- Creating a Frequency Plan for a System using a PLL
- RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs
- MING: An Automated CNN-to-Edge MLIR HLS framework
- Fault Tolerant Design of IGZO-based Binary Search ADCs