Embedded flash process enhances performance: Product how-to
Jae Song, Dongbu HiTek
EDN (August 23, 2014)
Mobile phones and tablets have become natural extensions of billions of users worldwide. Considered an essential companion by many, these gadgets continue to push performance limits as they integrate enhanced nonvolatile memory and ever smarter power management. Thanks to a new embedded Flash (eFlash) process, fabless chip designers can now economically integrate better performing nonvolatile memory into mobile chips while conserving power. The new process is especially well suited for embedding flash into Touch Screen Controllers (TSCs) and Micro Controller Units (MCUs).
The graphs that follow detail the key specifications for the new eFlash process at the 0.13 micron node. Fabless chip designers who seek to embed nonvolatile memory would be wise to consider these parameters before releasing their designs to a foundry.
To read the full article, click here
Related Semiconductor IP
- Flash Memory LDPC Decoder IP Core
- SPI Flash Controller - Ensures reliable validation of SPI Flash memory controllers
- Xccela Flash Memory Model
- Wide Range VCC Flash Memory Model
- Twin Quad NOR Flash Memory Model
Related Articles
- Product how-to: Reliable SoC bus architecture improves performance
- Product How-to: Fully utilize TSMC’s 28HPC process
- Using edge AI processors to boost embedded AI performance
- PRODUCT HOW-TO: Use ARM DBX hardware extensions to accelerate Java in space-constrained embedded apps
Latest Articles
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
- A 129FPS Full HD Real-Time Accelerator for 3D Gaussian Splatting
- SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation
- TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks