Flash Memory LDPC
Overview
LDPC corrects errors caused by flash storage failure mechanisms. The data is encoded while writing into the storage devices and it is decoded while reading from the storage devices. Decoding corrects read errors. The LDPC code that is used with storage devices should exhibit very low error floor (very low BER) and have high throughput.
Key Features
- Quasi cyclic (QC) – Algebraic constructed – LDPC code
- Regular parity check matrix
- Codeword length: 16 K
- Code rate: 0.953
- No or very low error floor
- Minimum sum algorithm
- Parallel/ Layered decoding
- Soft decision decoding
- Configurable number of iterations
Applications
- Flash Memory
Deliverables
- System Matlab model
- Synthesizable Verilog RTL
- Test Benches for verification
- Documentation
Technical Specifications
Maturity
Mature
Availability
Coming soon
Related IPs
- Flash Memory LDPC
- Fast Access Controller – a plug-and-play IP solution for fast embedded Flash Programming and Memory Testing
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- Hyperbus Flash Memory Controller
- Parallel FLASH Memory Controller
- Flash Memory LDPC Error Correction